1. Field of the Invention
The present invention relates to a semiconductor memory device, and particularly, to a semiconductor memory device precharging a single bit line from a plurality of sites.
Priority is claimed on Japanese Patent Application No. 2009-274494, filed Dec. 2, 2009, the content of which is incorporated herein by reference.
2. Description of the Related Art
In DRAMs (Dynamic Random Access Memories), data are stored by accumulating a charge in a capacitive element, readout of data from a memory cell and writing of data to the memory cell are performed through a bit line. However, particularly in the case of readout, it is necessary to differentially amplify data (memory information) read out from the memory cell using a sense amplifier and the like. For this reason, generally, there is a configuration using two bit lines as one set (bit line pair) and connecting them to input terminals of the sense amplifier, and signals complementary to each other are input to the sense amplifier through the bit line pair.
After the end of access to the memory cell, it is necessary to perform an operation of equalizing the potential of the bit line pair to the same potential level in preparation for next access, or a so-called precharge operation. This is because in a state where a difference occurs in the potential level of the bit line pair, when the memory cell, storing data different from the data of the memory cell previously accessed, in the same bit line is selected in the next access, an offset voltage is input to the sense amplifier, resulting in a malfunction.
On the other hand, since the cycle time of the DRAM is mostly occupied by the access time and the precharge time, it is important to shorten the precharge time of the bit line in order to achieve a shortening of the cycle time. However, in the DRAM, since the load of the bit line is weighted with high integration, the above-mentioned precharge time tends to be increased. Japanese Unexamined Patent Application Publication Nos. S61-126683 and S63-205897, for example, disclose a semiconductor memory device that precharges one bit line at a plurality of sites (including both ends). In addition, Japanese Unexamined Patent Application Publication No. 2004-79099 discloses a semiconductor memory device that precharges a global bit line from both ends thereof, with respect to the two-layer bit line of a local bit line and a global bit line. Japanese Unexamined Patent Application Publication No. H11-185481 discloses a semiconductor memory device including a connection transistor that short-circuits the bit line connected to a different sense amplifier, in other words, the unpaired bit line.